Method of forming a test insert for interfacing a device containing contact bumps with a test substrate

ABSTRACT

An insert is provided for testing a chip-scale-packaged microelectronic device having an encapsulant-protrusion and a ball-grid-array of outwardly-projecting contacts. The insert comprises a substrate of mono-crystalline silicon. Walls of the substrate define a plurality of pockets that are configured to receive and contact the outwardly-projecting contacts of the microelectronic device. Additional walls of the substrate define a recess disposed amongst the plurality of pockets. The recess has a width greater than the widths of any of the pockets. Additionally, the recess comprises a perimeter greater than that of the encapsulant-protrusion of the chip-scale-packaged microelectronic device, and a depth operative to clear the encapsulant-protrusion when the chip-scale package is seated upon the insert.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a test insert and method for testing a microelectronic device. More particularly, the present invention provides a silicon insert for testing a chip-scale-packaged electronic device having an encapsulant-protrusion and plurality of outwardly-projecting-contacts of a ball-grid-array.

[0002] A well known package of the microelectronics industry for semiconductor die comprises a molded epoxy package having a plurality of conductive pins that electrically interface the semiconductor die. More recently, however, the industry has developed smaller packages and interface solutions that use solder balls arranged in an array disposed on a surface of an electronic device. The array of solder balls, known as a ball-grid-array or bump-grid-array (BGA), permit smaller distances between adjacent input/output lines and provide for greater input/output density and lower costs for these devices.

[0003] One exemplary, prior art, package is the flip-chip, which comprises, with reference to FIG. 1, a plurality of outwardly-projecting electrical contacts 14 placed directly upon a face 18 of a semiconductor die 12. The flip-chip 9 does not require bond wires between bond pads of the die and a lead frame of the more conventional pin-type packages (not shown). The solder balls or outwardly-projecting-contacts 14 of the flip-chip are preferably of the same size, for example, in the range of 0.3 to 0.4 millimeters in diameter, and placed in an array having a distance between adjacent balls of, for example, about 1.5 mm. The advent of such BGA flip-chips led to the development of BGA test sockets.

[0004] Further referencing FIGS. 1-2, an exemplary prior art, BGA test socket 10 comprises a substrate 11 having a plurality of pockets 16 arranged in an array corresponding to the outwardly-projecting-contacts 14 of a flip-chip 9. A layer of conductive material 20 is formed and patterned over the substrate so as to provide conductive liners in pockets 16 and conductive traces over the substrate in electrical communication with the pockets. Such prior art, BGA test socket 10 is able to temporarily seat a flip-chip, microelectronic device and electrically engage the outwardly-projecting contacts of its BGA interface. During testing of the flip-chip packaged microelectronic device, the test socket and the flip-chip are biased together with pockets 16 of the test socket engaged with the outwardly-projecting-contacts 14 of the flip-chip.

[0005] Recent trends of the semiconductor industry have led to development of smaller size semiconductor die. At the same time, the number of input/output lines required for the die have remained the same or have increased, thereby increasing their input/output densities. To accommodate these input/output density enhancements, the semiconductor manufactures have developed alternative chip-scale packages.

[0006] One such alternative chip-scale-package is known as a “globbed” chip-scale-package. With reference to FIGS. 3A,3B,3C, “globbed” chip-scale-package 38 comprises a semiconductor die 12 mounted to an insulating support 32, also known as an interposer, which has an area about 1-2 times larger than die 12. Conductive lines 35 of interposer 32 electrically couple and reroute the small-size, fine-pitch, interposer pads 34 associated with die 12 to larger size, standard pitch, BGA contacts 14. The outwardly projecting contacts 14 of the interposer are designed in accordance, and for compliance, with conventional BGA standards.

[0007] Further referencing FIG. 3A, encapsulant protrusion 36 of globbed chip-scale-package 38, is disposed between and amongst a plurality of the outwardly protruding contacts 14 of the chip-scale-package. Encapsulant protrusion 36 comprises a material, e.g., non-conductive epoxy, suitable for enclosing interposer opening 31. Encapsulant protrusion 36 protects and encases bond-wires 30 which bond-wires bond-out and electrically couple terminals 29 of die 12 to conductive pads 34 of interposer 32. Encapsulant protrusion 36 of globbed chip-scale-package 38, with reference to FIG. 3C, usually has a height h₂ beyond the face of interposer 32 less than the height h₁ of the outwardly projecting contacts 14.

[0008] Prior art, BGA test inserts, for example the insert as shown in FIG. 1, may not provide reliable testing of the globbed chip-scale-packaged, microelectronic devices. When using such prior art, test insert to test globbed chip-scale-packaged, microelectronic devices, a region of upper surface 19 of the test insert may contact the encapsulant protrusion 36 of the globbed chip-scale-packaged microelectronic device, so as to interfer and prevent engagement of its outwardly projecting-contacts 14 with respective pockets 16 of the test insert 10.

[0009] What is needed is a BGA test socket for a globbed chip-scale-packaged, microelectronic device, which socket overcomes some of the problems of the prior art. What is also needed is a test insert capable of providing full and reliable, temporary electrical engagement with such microelectronic device. What is also needed is a method of reliably testing a globbed chip-scale-packaged, microelectronic device.

SUMMARY OF THE INVENTION

[0010] The present invention relates to the formation of an insert for engaging a microelectronic device having outwardly projecting contact bumps. The insert may be known by such terms as a receptacle, a BGA socket, an interconnect, a BGA test receiver, or silicon insert. The present invention recognizes and overcomes problems of the prior art caused by an encapsulant projection of a globbed chip-scale-packaged microelectronic device interfering with the interconnection of the insert with the outwardly projecting contacts of the chip-scale-packaged microelectronic device.

[0011] In accordance with one embodiment of the present invention, an insert is formed for seating and testing a chip-scale-packaged microelectronic device having a plurality of outwardly projecting contacts and a protrusion. The substrate is formed with walls that define a plurality of pockets configured to seat and engage the outwardly projecting contacts of the chip-scale-package. Other walls of the substrate define a recess configured to receive with clearance the encapsulant protrusion of the chip-scale-package when the outwardly projecting contacts are seated in the plurality of pockets.

[0012] In accordance with one aspect of this exemplary embodiment, the recess has a perimeter encompassing an area greater that that of a plurality of the pockets.

[0013] In accordance with another aspect of the exemplary embodiment, the recess of the insert is formed simultaneously with the pockets and of equal depth.

[0014] In accordance with another exemplary embodiment of the present invention, an insert comprises a substrate having walls that define a plurality of pockets that are configured to receive the outwardly projecting contacts of a microelectronic device. Other walls of the substrate may define vias that pass through the substrate and are in communication with associated pockets of the plurality. Conductive material fills the vias and lines a pocket connected to the via.

[0015] These and other features of the present invention will become more fully apparent in the following description and independent claims, or maybe learned by the practice of the invention as set forth hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention will be understood from reading the following description of the particular embodiments with reference to specific embodiments illustrated in the intended drawings. Understanding that these drawings depict only particular embodiments of the invention and are not therefore to be considered limiting of its scope, the invention will be described and explained with addition detail through use of the accompanying drawings in which:

[0017]FIG. 1 is a cross-sectional view of a known insert engaging a known BGA flip-chip component;

[0018]FIG. 2 is a planar elevational view of a known insert wire-bonded to an underlying support substrate, showing an array of pockets of the insert;

[0019]FIG. 3A is a cross-sectional view showing a known globbed chip-scale-packaged microelectronic device;

[0020]FIG. 3B is a cross-sectional view showing another globbed chip-scale-packaged microelectronic device of the prior art;

[0021]FIG. 3C is a partial cross-sectional view showing relative heights of an ecncapsulate protrusion and outwardly projecting contacts of a known, globbed chip-scale-packaged microelectronic device;

[0022]FIG. 4 is a cross-sectional view showing a globbed chip-scale-packaged microelectronic device seated upon an insert in accordance with an exemplary embodiment of the present invention;

[0023]FIG. 5 is a cross-sectional view showing a substrate and dielectric layer during formation of an insert in accordance with an embodiment of the present invention;

[0024]FIG. 6 is a cross-sectional view of the structure of FIG. 5 after further processing, showing patterned photoresist;

[0025]FIG. 7 is a cross-sectional view of the substrate and dielectric layer of FIG. 6 after further processing, showing a mask over the substrate;

[0026]FIG. 8 is a partial planar elevational view of the substrate of FIG. 7, showing an opening in a mask that exposes a region of the underlying substrate;

[0027]FIG. 9 is a cross-sectional view of the substrate of FIG. 7 after further processing, showing pockets and a recess;

[0028]FIG. 10 is a prospective view of the substrate of FIG. 9 after further processing has removed a mask;

[0029]FIG. 11 is a cross-sectional view of the semiconductor structure after further processing, showing conformal insulating and metal layers patterned over portions of the substrate including the pockets, and additionally showing the insert assembled within a test jig;

[0030]FIG. 12 is a partial planar elevation view showing a pocket of an insert;

[0031]FIG. 13 is a partial cross-sectional view illustrating a pocket of an insert engaging various size solder balls;

[0032]FIG. 14 is a cross-sectional view of a test jig showing a microelectronic device seated upon and pressed against a test insert in accordance with an embodiment of the present invention;

[0033]FIG. 15 is a partial cross-sectional view showing a pocket, via and micro-bump structure of a test insert over a support substrate in accordance with another embodiment of the present invention;

[0034]FIG. 16 is a partial cross-sectional view showing a substrate to be processed in accordance with a further embodiment of the present invention;

[0035]FIG. 17 is a schematic cross-sectional view of the structure of FIG. 16 after further processing, showing a mask over a substrate;

[0036]FIG. 18 is a representative cross-sectional view of the substrate of FIG. 17 after further processing, showing a pocket;

[0037]FIG. 19 is a cross-sectional view of the substrate of FIG. 18 after further processing, showing a via through the substrate and in communication with a pocket;

[0038]FIG. 20 is a cross-sectional view of the substrate of FIG. 19 after further processing, showing a conformal layer of insulating material over the substrate including the walls of the via and pockets;

[0039]FIG. 21 is a cross-sectional view of the substrate of FIG. 20 after further processing, showing two layers of conductive material over the substrate;

[0040]FIG. 22 is a cross-sectional view of the substrate of FIG. 21 after further processing, showing mask material over regions of the substrate associated with a pocket;

[0041]FIG. 23 is a cross-sectional view of the substrate of FIG. 22 after further processing, showing patterned conductive layers;

[0042]FIG. 24 is a cross-sectional view of the substrate of FIG. 23 after further processing, showing the via filled with conductive material and the pocket lined with the conductive material;

[0043] FIGS. 25-28 are schematic cross-sectional views illustrating a method of forming a solder bump over a via filled with conductive material in accordance with an exemplary embodiment of the present invention; and

[0044]FIG. 29 is a cross-sectional view of a test jig for testing a microelectronic device seated upon and pressed against a test insert.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] Reference will now be made to drawings wherein like structures are provided like reference designations. The drawings are representative, non-limiting diagrams of select embodiments of the present invention and are not necessarily drawn to scale.

[0046] The present invention relates to formation of an insert for receiving and testing a “globbed” chip-scale-packaged microelectronic device having an array of outwardly projecting contacts, e.g., of a ball-grid-array or bump-grid-array (BGA). Such insert may also be known by other terms such as, for exemple, interconnect, interposer, socket, BGA test socket, or silicon insert.

[0047]FIG. 1 shows a cross-sectional view of a known flip-chip 9 seated upon a known insert 10. Solder balls or outwardly projecting contacts 14 of flip-chip 9 engage pockets 16 of insert 10. Inwardly facing surface 18 of flip-chip 12 is kept in spaced relationship over surface 19 of insert 10. Patterned conductive material 20 of the insert electrically couple pockets 16 to their associated pads 21 around the periphery of the insert 10. Typically, dielectric 22 insulates conductive material 20 from substrate 11. Bonds wire 28 electrically couple the peripheral pads 21 of insert 10 to conductive pads 24 of support substrate 26.

[0048] A planar elevational view, with reference to FIG. 2, shows pockets 16 of insert 10 arranged in an array, which would correspond to the BGA structure of a flip-chip (shown in phantom lines). Providing additional detail, conductive traces 25 of patterned conductive material 20 of insert 10, electrically couple pockets 16 to the pads 21 around the periphery of insert 10, while bond wires 28 bound-out pads 21 of the insert to the conductive pads 24 of support substrate 26.

[0049] Recent trends of the semiconductor industry have reduced semiconductor die size, while increasing the number of input/output interconnects. These changes have lead to development of newer ball-grid-array or bump-grid-array (i.e., BGA) interface solutions cpable of accommodating the smaller die of increased I/O densities. One such exemplary, prior art, BGA interface package comprises the globbed chip-scale-package.

[0050] Referencing FIG. 3A, globbed chip-scale-packaged microelectronic device 38 comprises a semiconductor die 12 disposed over insulating support 32. Walls 31 of support 32 define an opening through which bond wires 30 bond-out contacts 29 of die 12 to pads 34 of support 32. Outwardly projecting contacts or solder balls 14 of support 32 are disposed across its outwardly facing surface 18, and arranged in an array or grid in compliance with BGA industry standards. Encapsulation material 36, such as epoxy, seals opening 31 for protecting bond wires 30 and die 12. Hereinafter, encapsulation material 36 is referred to as an “encapsulant projection”. Although shown having a rounded upper surface, encapsulant projection 36 may comprise alternative shapes, such as, for example, a squared profile as might be provided by a mold.

[0051] In FIG. 3A, contacts 29 of semiconductor die 12 are located near a center region of the die. Alternatively, with reference to FIG. 3B, the contacts of die 12 might be located near a peripheral edge of the die. To accommodate this alternative embodiment, an alternative support 32 comprises a recess 13 that seats die 12 therein. Bond wires 30 electrically interface the peripheral pads of the die to pads 34 of the interposer 32 proximate recess 13. Conductive traces 35 of the support couple and re-route the central pads 34 to alternatively positioned outwardly projecting-contacts 14. With reference to FIG. 3C, the outwardly projecting contacts 14 of the chip-scale-package 38 have a height h₁ greater than the height h₂ of encapsulant projection 36. In an exemplary embodiment, outwardly projecting contacts 14 have a height h₁ of about 0.35 millimeters (about 0.8 times its width or “diameter”), and encapsulant projection 36 a height h₂ of about 0.1 to 0.3 millimeters.

[0052] Continuing with reference to FIGS. 3A-3C, when trying to seat such globbed chip-scale-packaged microelectronic device 38 over prior art BGA test inserts—i.e., an insert similar to that of FIG. 1—the encapsulant projection 36 of the package may confront a region of the upper surface of the insert to as to interfere with and prevent the outwardly projecting contacts 14 of the device from engaging respective pockets 16 of the prior art insert.

[0053] Recognizing this potential difficulty, the present invention proposes a new test insert having a recess configured to receive with clearance a protrusion of such chip-scale-package. In an exemplary embodiment of the present invention, with reference to FIG. 4, insert 10 comprises recess 17 having a peripheral outline and depth capable of receiving with clearance an encapsulant projection of a globbed chip-scale-packaged microelectronic device while the outwardly projecting contacts of the device are seated in pockets 16 of the insert. In a further exemplary embodiment, insert 10 forms part of a test jig for testing such globbed chip-scale-packaged devices. Wire bonds or flex-tab-tape electrically couple insert 10 to support substrate 26 which, in turn, is in electrical communication with an external test system (not shown in FIG. 4). A method of forming such insert, in accordance with another exemplary embodiment of the present invention, is now described below with reference to FIGS. 5-13.

[0054] Referencing FIG. 5, substrate 40 comprises a semiconductor substrate, a dielectric substrate, or a layered combination thereof. Suitable exemplary substrates include silicon-on-glass, silicon-on-sapphire, germanium, gallium arsenide, or ceramic. In the current application, the term “substrate” will be understood to mean any supporting structure including, but not limited to, semiconductor substrates. Further, the term “substrate” or “semiconductor substrate” may also refer to any construction comprising semiconductor material, including but not limited to bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).

[0055] In a preferred exemplary embodiment, further referencing FIG. 5, substrate 40 comprises mono-crystalline silicon having a <100> crystalline lattice-plane at surface 19 and a thickness of at least 500 μm, and more preferably a thickness between 650 to 750 μm. Etch resistant material 42 such as silicon nitride is formed over surface 19 of substrate 40. Etch resistant material 42 is provided a thickness greater than 100 angstroms, and more preferably between 500 to 3000 angstroms, and is formed using known means such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0056] Moving on to FIG. 6, photoresist 44 is patterned over etch resistant material 42 using known photolithographic procedures to provide openings that expose corresponding regions of etch resistant material 42. Through these openings of the patterned photoresist 44, the exposed regions of the etch resistant material 42 are removed and openings 46 formed in the layer of etch resistant material (hereinafter mask 42) as shown in FIGS. 7-8.

[0057] Referencing FIG. 9, exposed regions of substrate 40 are then etched through the mask openings 46 to form pockets 16 and recess 17 within the substrate. In a preferred exemplary embodiment, where substrate 40 comprises mono-crystalline silicon having a <100> lattice-plane of orientation at surface 19, a potassium hydroxide (KOH) etch solution is used to anisotropically etch the substrate. Using such anisotropic etchant, pockets 16 and recess 17 are formed with sidewalls having a slope of between 40° to 70°, and typically 54° relative a plane defined by the substrate's surface 19.

[0058] Continuing with reference to FIGS. 9 and 10, recess 17 and pockets 16 are preferably etched simultaneously with a depth of at least 10 μm, and more preferably between 15 to 150 μm. Additionally, the sidewalls that define recess 17 meet surface 19 of the substrate to define a peripheral outline 15 encompassing an area greater that that of any individual pocket 16, and more preferrably, greater that that of a plurality of the pockets. For example, pockets 16 are formed with a width between 100 to 400 μm, and more preferably between 200 to 350 μm, while recess 17 provided a width of at least 500 μm and more preferably between 2,000 to 3,000 μm, and a length preferably between 4,000 to 15,000 μm. In a preferred exemplary embodiment, pockets 16 have widths slightly less than the diameter of the outwardly projecting contacts of the microelectronic to be seated therein.

[0059] After the etching the pockets 16 and recess 17, mask 42 is removed and a dielectric 22—for example, an oxide, nitride, carbide or the like formed conformably over substrate 40, see FIG. 11. Dielectric 22 is formed by a known deposition process such as, for example, chemical vapor deposition (CVD).

[0060] Preferably, dielectric 22 comprises silicon dioxide formed by thermal oxidation of underlying a silicon substrate 40. In such an exemplary embodiment, substrate 40 comprises silicon and is exposed to an oxidizing atmosphere comprising steam and oxygen at an elevated temperature (e.g. 950°). The oxidizing atmosphere oxidizes exposed portions of substrate 40 and forms an oxide layer conformally over the substrate's exposed surfaces. In an alternative embodiment, dielectric 22 is formed by thermal decomposition of tetraethylortho-silicate (TEOS). Preferably, the dielectric (hereinafter, insulating layer 22) is formed with a thickness of between 0.5 to 5 μm.

[0061] Conductive layer 20 is formed over the insulating layer 22 and in each of pockets 16. The conductive layer is patterned to provide conductive liners in pockets 16. The pockets (with conductive liners) are configured to engage the outwardly projecting contacts of a chip-scale-packaged microelectronic device for enabling electrical communication with the microelectronic device when seated thereon. In a preferred exemplary embodiment, regions of the originally deposited conductive layer 20 associated with recess 17 are removed. Alternatively, regions of the conductive material within recess 17 can be patterned to provide conductive traces within the recess.

[0062] Conductive layer 20 may comprise material of group IIIB through VIIIB metals, such as (but not limited to) the refractory metals, e.g., aluminum, iridium, copper, titanium, tungsten, tantalum, molybdenum, or alloys thereof. Conductive layer 20 might alternatively comprise other electrically conductive material such as, for example, metal-nitride of titanium-nitride or a silicide such as titanium-silicide. In a preferred exemplary embodiment, conductive layer 20, at regions associated with pockets 16, comprises an upper layer of titanium over a lower layer of aluminum. The upper layer selected to prevent permanent or chemical bonding of the pocket liners to the conductive material of the outwardly projecting contacts to be seated thererin. These conductive materials may be formed using known metal deposition processes, e.g., sputter, CVD, or PVD deposition. Additionally, the conductive materials can be patterned using known photolithographic, masking and etch procedures.

[0063] In another exemplary embodiment, conductive layer 20, at regions associated with bond pads 21, comprises a stack of two different layers, e.g., a lower barrier layer and an upper bonding layer to which wire bonds may be attached, as set forth in U.S. Pat. No. 5,592,736, issued Jan. 14, 1997, entitled “Fabricating An Interconnect For Testing Unpackaged Semiconductor Dice Having Raised Bond Pads”, which is hereby incorporated by reference. See also U.S. patent application Ser. No. 09/110,554 filed Jul. 6, 1998, entitled “Metalized Recess In A Substrate And Method Of Making The Same”, which is also incorporated herein by reference. In particular, the barrier and bonding layers are formulated to prevent oxidation of conductive materials associated with the interconnects, which oxidation might otherwise change the resistance of its contacts. The bonding layer is selected to facilitate wire bonding thereto. In a preferred exemplary embodiment, the barrier layer comprises a metal such as platinum, titanium, tungsten, or alloys thereof. As patterned, certain portions of conductive layer 20 define traces 23 while other portions define bond pad 21 in electrical communication with the conductive liners of pockets 16. Methods of forming the conductive material, traces and liners can be found in U.S. patent application Ser. No. 09/110,554, filed Jul. 6, 1998, entitled “Metalized Recess In A Substrate And Method Of Making The Same”, again incorporated herein by reference. In other more specific exemplary embodiments, regions of the conductive layer 20 associated with the bond pads may comprise multiple layers of conductive material such as, for example, a four layer stack (not shown) comprising titanium, tungsten, titanium and aluminum respectively.

[0064] In an exemplary embodiment, further referencing FIG. 11, bond pads 21 of insert 10 comprise a metal, such as aluminum or an aluminum-titanium stack, deposited over select regions of conductive layer 20. In an alternative embodiment, the bonding pads are patterned from a portion of conductive layer 20. These bond pads 21 serve as electrical interface terminals for insert 10. Wire bonds, tab tape, or other suitable connection means are coupled to the bond pads of the insert and provide electrical communication to external circuitry.

[0065] In a preferred exemplary embodiment, with reference to FIGS. 12-13, pockets 16 of the insert include known blade structures 48. Blade structures 48 allow pockets 16 to engage both small solder balls 14′ or large solder balls 14 (shown in phantom lines). Accommodating a variety of solder ball dimensions, these pockets with blade structures facilitate reliable engagement and electrical coupling to BGA packaged microelectronic devices. U.S. Pat. No. 5,592,736, again incorporated herein by reference, provides additional information regarding such blades 48, and, in particular, teaches blade configurations that penetrate the outwardly-projecting contacts of a microelectronic device to a predetermine depth less than the height of the outwardly projecting contacts, while, at the same time, minimizing surface damage and spreading of the outwardly projecting contacts.

[0066] Returning to FIG. 4, a globbed chip-scale-packaged microelectronic device 38 is seated upon insert 10. Recess 17 of the insert comprises a peripheral outline greater than that of the encapsulant projection, and a depth preferably equal to that of pockets 16. Accordingly, during test of the globbed chip-scale-packaged microelectronic device, recess 17 is able to receive the encapsulant projection of the microelectronic device without contact, so as not to interfere with the mechanical coupling and electrical connection of pockets 16 with the outwardly projecting contacts 14 of the microelectronic device.

[0067] In accordance with another exemplary embodiment of the present invention, with reference to FIG. 14, a test jig 59 comprises an insert 10 within an assembly for testing a globbed chip-scale-packaged microelectronic device 38. Insert 10 is fixed to support substrate 26, which in-turn is fixed to a test head or base 48. Globbed chip-scale-packaged microelectronic device 38 is positioned over insert 10, with outwardly projecting contacts 14 seated and engaged with their respective pockets 16 of the insert. Encapsulant projection 36 of the microelectronic device extends into recess 17 of the insert without contacting walls that define the recess. Wire bonds 28 couple conductive pads of insert 10 to conductive pads of support substrate 26. Socket contacts 46 of the test jig electrically couple the circuit traces of the support substrate to terminal leads 47, which terminal leads are in electrical communication with test circuitry 58 by way of bus 60.

[0068] In the illustrated exemplary embodiment, cover 54 acts together with biasing member 52 and force plate 50 to apply a biasing force against the globbed chip-scale-packaged microelectronic device 38, thereby forcibly engaging its outwardly projecting contacts 14 against pockets 16 of insert 10. Cover 54 includes clips 53 and tabs 57. Tabs 57, at the ends of clips 53, are received and captured by clamp ring 56 for securing the cover 54 to base 48. Cover 54 preferably comprises resilient metal, such as steel. Force plate preferably comprises a solid material such as metal, plastic or ceramic. The force plate is shaped to engage and apply a force across various surfaces of the globbed chip-scale-packaged microelectronic device 38. Biasing member 52 is disposed between the inside surface of cover 54 and force plate 50 to apply a force against force plate 50 when cover 54 is secured to base 48. Biasing member 52 preferably comprises a resilient elastomeric material—e.g., silicone, butyl rubber, flourosilicone, and polyimide—capable of exerting a biasing force over a continued life-span. Additional aspects concerning elements of test jig 59 and its assembly are provided by U.S. patent application Ser. No. ______, filed ______, entitled “Test Carrier With Variable Force Applying Mechanism For Testing Semiconductor Components” (98-0333), and U.S. Pat. No. 5,796,264 entitled “Apparatus For Manufacturing Known Good Semiconductor Die”, which application and patent are incorporated herein by reference.

[0069] In accordance with another exemplary embodiment of the present invention, with reference to FIG. 15, a silicon insert 10 comprises a via filled with conductive material 62 connected to an underlying solder bump 66. Solder bump 66 is coupled to a surface 75 of the conductive material 62 within the via opening where walls 63 of the via meet surface 41 of substrate 40. The filled via provides electrical communication between pocket 16 and solder bump 66. Solder bump 66 of the insert is disposed over conductive pad 68 of support substrate 26. Conductive material 62 comprises metal wetable by molten solder of solder bump 66. Likewise, conductive pad 68 of support substrate 26 also comprises metal wetable by the reflow of such solder. Accordingly, a step of heating solder bump 66 will re-flow the solder of the solder bump and wet pad 68 for joining the insert to the supporting substrate. During such reflow, the surface tension and cohesive forces of the molten solder reshape the solder, e.g., as illustrated by phantom lines 70. This insert of FIG. 15 is capable of efficient manufacture by way of another exemplary embodiment of the present invention described below with reference to FIGS. 16-18.

[0070] Referencing FIGS. 16-18, mask 42 is formed over substrate 40 using a known method of mask formation. Substrate 40 preferably comprises monocrystalline silicon having a <100> lattice-plane of orientation at surface 19. Exposed portions of substrate 40 (i.e., exposed per openings 46 of mask 42) are etched to form pockets 16 in the substrate. In an exemplary embodiment, the substrate is etched using an anisotropic etchant—e.g., a mixture of potassium hydroxide (KOH) and water. With such anisotropic etchant, the <100> silicon lattice-surface of the substrate etches more rapidly than the other orientations so as to form sidewalls for the pockets having a slope of between 40 to 70 degrees, and typically 54 degrees, relative a plane defined by surface 19 of substrate 40.

[0071] As described before relative FIGS. 4-11, preferably, a recess (not shown in FIGS. 16-28) is formed in substrate 40 simultaneously with pockets 16. In such aspect, the pockets are configured to seat the outwardly projecting contacts of a BGA component, and the recess configured to receive with clearance a protrusion of a BGA component.

[0072] Continuing with the present embodiment with reference to FIG. 19, the substrate is further processed to form via 61 between a floor of pocket 16 and lower surface 41 of substrate 40. Via 61 comprises sidewalls 63 preferrably centered about a center axis (not shown) of pocket 16. However, in alternative embodiments (not shown), via 61 is positioned away from the center-axis of pocket 16. In a preferred exemplary embodiment, via 61 is formed with sidewalls 63 substantially perpendicular (90°) to lower surface 41 of substrate 40, and with a diameter of about 30-150 μm.

[0073] In the exemplary embodiment, via 61 is formed using a laser machine. A suitable laser machine to form via 61 is a laser machine manufactured by General Scanning of Summerville, Mass., designated by Model No 670-W. In an exemplary embodiment, the laser power to form via 61 through a substrate of silicon (e.g., of 28 mil thickness) is a power of about 2-10 watts per opening, at a pulse duration of about 20-25 ns, and repetition rate of up to several thousand pulses per second. The spectrum for the laser beam can be standard infrared or green (e.g., 10.6 μm to 532 μm wavelength). Preferably, the laser beam is generated by a NdYag or CO₂ laser of about 10.6 μm wavelength.

[0074] After forming via 61 in communication with pocket 16, referencing FIG. 20, a dielectric 22 is layered conformably over substrate 40. In a particular embodiment, substrate 40 is exposed to an oxidizing environment to form an oxide dielectric 22 conformably over substrate 40, including the walls defining pocket 16 and via 61. The oxidizing atmosphere, in an exemplary embodiment, comprises steam and oxygen (O₂) at an elevated temperature of, for example, 950° C. Preferably, dielectric 22 is formed with a thickness in a range of 0.5 to 5 μm. In alternative embodiments, where substrate 40 comprises an electrically insulating material, such as ceramic or a glass filled resin, the formation of the dielectric insulating layer 22 may be eliminated.

[0075] Referring now to FIG. 21, a first conductive material 62 is formed conformably over substrate 40, including via 61 and the walls of pockets 16. In an exemplary embodiment, conductive material 62 fills via 61 and comprises metal wetable by solder. Preferably, conductive layer 62 comprises copper of at least 5 μm thickness, and more preferably, a thickness between 15-75 μm. Alternative metals for conductive material 62 include gold, palladium, nickel, chromium, or alloys thereof.

[0076] After forming conductive material 62, second conductive material 64 is formed over first conductive material 62, with a thickness greater than 500 angstroms and, more preferably, 600 to 20,000 angstroms. The second conductive material comprises material different from the first conductive material 62 and is selected to resist bonding to solder. In certain exemplary embodiments, second conductive material 64 comprises a metal such as tungsten, titanium, platinum, titanium nitride or titanium-tungsten. Conductive layers 62,64 are formed using known deposition processes, such as, for example, CVD, PVD, electrolytic or electrolysis deposition.

[0077] Continuing with reference to FIGS. 22-24, mask 72 is formed over the conductive layers and patterned appropriately to cover regions of the conductive materials associated with pockets 16. Mask 72 comprises known masking material, e.g., photoresist, nitride or other suitable mask material. With mask 72 over pockets 16, exposed regions of the conductive material are etched using known wet or dry etchants until exposing insulating layer 22 (or alternatively substrate 40). Next, mask 72 is removed, leaving pockets 16 lined with conductive material 62 and 64 as shown by FIG. 24.

[0078] Moving on to FIGS. 25-28, a micro-bump 66 (referred to alternatively before relative to FIG. 15 as a solder bump) is formed over surface 41 of substrate 40 and in contact with exposed surface 75 of conductive material 62 in via 61. In a preferred exemplary embodiment, via 61 has a diameter of 30-150 μm. Additionally, micro-bump 66 comprises a metal alloy—e.g., a lead/tin (PbSn) solder or alloy of indiun/tin (InSn) or antimony/tin (SbSn)—that is formed on the outwardly facing surface 75 of the conductive material 62 at the via's opening.

[0079] In alternative exemplary embodiments, micro-bump 66 comprises metal of the group consisting of copper, nickel, gold and platinum, and is formed using known equipment and methods of the art, including for example selective deposition, electro-plating, electroless-plating, screen-printing or evaporation. U.S. Pat. No. 5,808,360, entitled “Micro Bump Interconnect For Bare Semiconductor Dice”, issued Sep. 15, 1998, incorporated herein by reference, provides description of such exemplary micro-bump structures and formation. One such method of forming micro-bumps is now described below with reference to FIGS. 25-28.

[0080] Referencing FIGS. 25-26, stencil 78 is positioned over surface 41 of substrate 40 and comprises opening 77 that is positioned over via contact 75. Via contact 75 is understood to mean, and was referred to before as, the outwardly facing surface 75 of the conductive material 62 within the via opening where walls 63 of via 61 meet surface 41 of substrate 40. Continuing with the present embodiment, a solder drop 72 is dispensed from a nozzle 74 over stencil 78 proximate the stencil's opening 77. Squeegee-blade 80 (FIG. 26) squeegees drop 72 across and into opening 77 of stencil 78. The height and width of opening 77 are selected in accordance with a desired solder volume for micro-bump 66. In an exemplary embodiment, opening 77 provides a pocket volume of about 0.032 mm³.

[0081] Continuing with FIGS. 27-28, the stencil is removed, leaving stenciled solder 76 over and in contact with via contact 75, the outwardly facing surface of the conductive material 62 at the via's opening. Thereafter, heat is applied to the stenciled solder 76 so as to reflow the solder and form a rounded shape for micro-bump 66. In an exemplary embodiment, the solder comprises a lead/tin eutectic and is heated to a re-flow temperature of about 183° C. In an alternative embodiment, the solder comprises a 95:5 lead/tin mixture and is heated to a reflow temperature of about 320° C. During the re-flow, it is theorized that the surface tension and cohesive forces of the molten solder provide the forces operative to reshape the solder into a hemispherical or generally convex shape.

[0082] In a test jig, referencing FIGS. 15 and 29, silicon insert 10 is positioned over support substrate 26 with the micro-bumps 66 over their pads 68 of the support substrate 26. Thereafter, heat is applied to re-flow the solder microbumps 66 for wetting pads 68 of the support substrate and securing silicon insert 10 to support substrate 26. Support substrate 26 and silicon insert 10 can then be employed in a test system, such as that portrayed by FIG. 29, for testing a microelectronic device 38 having an array of outwardly projecting contacts 14.

[0083] For the exemplary test system illustrated by FIG. 29, test circuitry 58 sends electrical signals to the device under test by way of bus 60, terminal leads 47, conductive traces 24 of support substrate 26, micro-bumps 66, via 61 and lined pockets 16 of insert 10. As described before relative FIG. 14, cover 54 clips into clamp ring 56 by way of tabs 57 for compressing biasing member 52 to provide a force against force plate 50 which presses outwardly projecting contacts 14 of microelectronic device 38 into pockets 16 of the silicon insert 10.

[0084] Thus, the present invention provides a new insert, method for forming an insert and method of testing a globbed chip-scale-packaged microelectronic device. Although the foregoing invention has been described with respect to certain exemplary embodiments, other embodiments will become apparent in view of the disclosure herein. Accordingly, the described embodiments are to be considered only as illustrative and not restrictive. The scope of the invention, therefore, is indicated by the appended claims and there combination in whole or in part rather than by the foregoing description. All changes thereto which come within the meaning and range of the equivalent of the claims are to be embraced within the scope of the claims. 

What is claimed is:
 1. An insert for seating an electronic device comprising a chip-scale package having electrical-contact bumps and a protrusion prjecting from a common side thereof, said insert comprising: a substrate having walls defining a plurality of pockets configured to receive at least a portion of the electrical-contact bumps of said chip-scale-package, other walls of said substrate defining a clearance recess configured to receive with clearance the protrusion of said chip-scale-package when the electrical contact bumps are at least partially received in said plurality of pockets; and conductive material within at least a portion of at least some of said plurality of pockets.
 2. An insert according to claim 1 , wherein said recess has a perimeter encompassing an area greater than any of said pockets.
 3. An insert according to claim 2 , wherein said pockets each have a width less than 400 μm and said recess has a width greater than 500 μm.
 4. An insert according to claim 3 , wherein said pockets each have a width between 100-400 μm, and said recess a width between 2,000-3,000 μm and length between 4,000 to 15,000 μm.
 5. An insert according to claim 3 , wherein said pockets and said recess have substantially the same depth.
 6. An insert according to claim 5 , wherein said depth is at least 10 μm.
 7. An insert according to claim 3 , wherein said pockets and said recess have a depth between 15-150 μm.
 8. An insert according to claim 2 , wherein said recess is disposed between at least two pockets of said plurality of pockets.
 9. An insert according to claim 1 , wherein said substrate comprises monocrystaline silicon.
 10. An insert according to claim 9 , further comprising a layer of dielectric material disposed conformably against said silicon of said substrate and beneath said conductive material.
 11. An insert according to claim 10 , wherein said dielectric material comprises an oxide.
 12. An insert according to claim 10 , wherein said conductive material comprises at least one of the group consisting of refractory metal, refractory metal nitride, and refractory metal salicide.
 13. An insert according to claim 1 , wherein said conductive material comprises at least one of the group consisting of group IIIB through VIIIB metals.
 14. An insert according to claim 13 , wherein said conductive material that lines said pockets is selected to resist bonding to the outwardly-projecting electrical-contact bumps of said chip-scale-package.
 15. An insert according to claim 1 , wherein said conductive material that lines said pockets is selected to resist bonding to solder.
 16. A ball-grid-array socket for seating a microelectronic device having an array of contact-bumps and a protrusion projecting from a common side thereof, said ball-grid-array socket comprising: a substrate with a primary surface having a plurality of pockets disposed in a pattern thereacross corresponding to said array of contact-bumps of the microelectronic device, said pockets configured to at least partially receive said contact-bumps of the microelectronic device, said primary surface of said substrate further defining a recess configured to receive and clear the protrusion of the microelectronic device when the contact bumps are at least partially received in respective said pockets of said substrate, said recess disposed amongst said plurality of pockets; and electrically conductive material layered conformably over at least a portion of said substrate including at least some of said plurality of pockets.
 17. A ball-grid-array socket according to claim 16 , wherein said substrate comprises monocrystaline silicon.
 18. A ball-grid-array socket according to claim 17 , further comprising a layer of dielectric disposed conformably against said silicon substrate and beneath said electrically conductive material.
 19. A ball-grid-array socket according to claim 18 , wherein said dielectric comprises an oxide.
 20. A ball-grid-array socket according to claim 17 , wherein said silicon has a <100> lattice-plane of orientation at said primary surface.
 21. A ball-grid-array socket according to claim 16 , wherein said walls defining said pockets are sloped with an angle of about 40-70 degrees relative a plane defined by said primary surface.
 22. An interconnect for electrically interfacing an electronic component, said electronic component having a protrusion and a plurality of outwardly-projecting contact-bumps extending outwardly from a front surface thereof, said interconnect comprising: a substrate having a primary surface with a plurality of pockets configured to at least partially contact respective said outwardly-projecting contact-bumps of said electronic component, said primary surface further having a clearance recess configured to receive with clearance the protrusion of the electronic component when said contact-bumps are at least partially contacting associated said plurality of pockets; and conductive material patterned over at least a portion of the primary surface of said substrate and extending into at least one of said plurality of pockets.
 23. An interconnect according to claim 22 , wherein said pockets associated with respective said outwardly-projecting contact-bumps each have a first width, said protrusion has a second width greater than said first width, and said clearance recess has a width greater than said second width for enabling clearance of said protrusion.
 24. An interconnect according to claim 23 , wherein said clearance recess has a depth of at least 10 μm.
 25. An interconnect according to claim 24 , wherein said substrate comprises silicon.
 26. An interconnect according to claim 25 , wherein said silicon has a <100> plane of orientation at said primary surface.
 27. An interconnect according to claim 25 , wherein said substrate has a thickness of at least 500 μm.
 28. An interposer for interfacing an electronic component having a protrusion and a plurality of contact-bumps that extend outwardly from a front face thereof, said interposer comprising: a substrate having a primary surface with a plurality of pockets disposed thereacross, said plurality of pockets configured to at least partially receive respective said plurality of contact-bumps of said electronic component, said primary surface further comprising a recess configured to receive with clearance the protrusion of the electronic component when said contact-bumps are at least partially received within associated said plurality of pockets; conductive material patterned over the primary surface of said substrate including at least one of said plurality of pockets; and an electrical terminal disposed on said substrate and electrically coupled to said at least one pocket by a portion of said patterned conductive material.
 29. An interposer according to claim 28 , wherein said substrate comprises silicon.
 30. An interposer according to claim 29 , wherein said silicon has a <100> lattice plane of orientation at said primary surface.
 31. An interposer according to claim 30 , wherein said walls that define said pockets have a slope of about 40-70° relative said primary surface.
 32. An interposer according to claim 31 , wherein said one pocket that receives said protrusion has a depth of at least 10 μm.
 33. An interposer according to claim 32 , further comprising a dielectric layer conformably layered over said substrate and beneath said patterned conductive material.
 34. An interposer according to claim 33 , wherein said dielectric comprises oxide.
 35. An interposer according to claim 33 , wherein said substrate has an outer peripheral edge and said electrical terminal is disposed proximate said outer peripheral edge.
 36. A method of interfacing an electronic device comprising the steps of: providing an electronic device having a plurality of contact-bumps of a ball-grid-array and an encapsulant projection that extend outwardly from a face thereof; providing a substrate having a primary surface with a plurality of pockets disposed thereacross corresponding to said plurality of contact-bumps of the ball-grid-array of said electronic device, said primary surface further comrising a recess; disposing said electronic device over said substrate; contacting at least part of each of said contact-bumps of said electronic device with respective said plurality of pockets of said substrate; and receiving and clearing said encapsulant projection of said electronic device within said recess of said substrate.
 37. A method according to claim 36 , further comprising a step of propagating an electrical signal between said substrate and said electronic device.
 38. A method according to claim 37 , wherein said step of propogating includes transferring said electrical signal between a contact-bump of the electronic device and the respective pocket of said plurality engaged therewith.
 39. A method of testing an electronic device comprising steps of: providing a chip-scale-packaged electronic device, said chip-scale-package having a protrusion and a plurality of outwardly-projecting contact-bumps that extend outwardly from a face thereof; providing a substrate having walls that define a plurality of pockets across a surface thereof, at least one of said plurality of pockets configured to at least partially receive respective one of said plurality of contact-bumps of the chip-scale-package, other walls of said substrate defining a recess configured to receive the protrusion of the electronic device; coupling said electronic device to said substrate with said at least one contact bumps at least partially contacting associated said plurality of pockets and said protrusion positioned within said recess without contacting the walls defining said recess; and propagating at least one electrical signal between said substrate and said electronic device.
 40. A method according to claim 39 , further comprising a step of removing said electronic device from said substrate after propagating the electrical signal.
 41. A method according to claim 39 , wherein an electrical signal is propagated between a contact-bump of the electronic device and a pocket of said substrate.
 42. A method of fabricating an insert for interfacing an electronic device having a plurality of contact-bumps and a protrusion that extend outwardly from a face thereof, said method comprising the steps of: providing a substrate; forming a plurality of pockets in said substrate; forming a recess in said substrate having a width and length, the width and length of said recess being greater than the respective widths of any of said pockets; forming a layer of insulating material conformably over said substrate, including said plurality of pockets; and forming conductive material over said insulating material, including at least a portion of said pockets.
 43. A method according to claim 42 , wherein said plurality of pockets and said recess are formed in a single step of etching.
 44. A method according to claim 43 , wherein said step of etching comprises an anisotropic wet etch.
 45. A method according to claim 44 , wherein said substrate comprises monocrystalline silicon with a <100> surface plane.
 46. A method according to claim 43 , wherein said pockets and said recess are formed with a depth of at least 10 μm.
 47. A method according to claim 46 , wherein said pockets and said recess are formed with a depth of about 15-150 μm.
 48. A method according to claim 42 , wherein said step of forming the conductive material over said substrate comprises the steps of: layering metal conformably over said substrate; and clearing portions of said metal from regions of said substrate corresponding to said recess.
 49. A method of fabricating a ball-grid-array socket for an electronic device comprising a chip-scale-package having an array of outwardly-projecting contact-bumps and an encapsulant-projection, said method comprising the steps of: providing a substrate; etching said substrate and forming a trench in said substrate and an array of pits in said substrate disposed on at least two opposite sides of said trench, said array of pits formed to at least partially contact respective said outwardly-projecting contact bumps of said chip-scale-packaged electronic device and said trench formed with a length and a width greater than that of any pit of said plurality to enable receipt with clearance of the encapsulant-protrusion of said chip-scale-packaged electronic device; forming an insulating layer conformably over said substrate, incuding said pits; forming conductive material in at least some of said pits; and forming a conductive trace on the substrate in electrical communication with the conductive material of at least one of said pits.
 50. A method according to claim 49 , wherein said step of etching comprises an anisotropic wet etch.
 51. A method according to claim 50 , wherein said substrate comprises monocrystalline silicon having a <100> surface plane.
 52. A method according to claim 49 , wherein said pit and trench are formed with a depth of at least 10 μm.
 53. A method according to claim 52 , wherein said pit and trench are formed with a depth in the range of 15-150 μm.
 54. A method according to claim 49 , further comprising a step of forming a via in said substrate.
 55. A method according to claim 54 , wherein said via is formed in communication with a pit of said array of pits.
 56. A method according to claim 54 , wherein said via is formed between a floor of a pit of said array of pits and a surface of said substrate opposite said array of pits.
 57. A method according to claim 54 , wherein said step of forming the via employs a laser beam.
 58. A method according to claim 54 , wherein said via is formed with walls substantially perpendicular to a surface of said substrate.
 59. A method according to claim 58 , wherein sidewalls of said array of pits are formed with a slope between 40-70° relative said surface of said substrate.
 60. A method according to claim 54 , wherein said step of forming the insulating layer includes coating sidewalls of said via with insulating material.
 61. A method according to claim 60 , wherein said step of forming the insulating layer comprises a step of exposing said substrate to an oxidizing environment.
 62. A method according to claim 54 , further comprising a step of forming conductive material within said via.
 63. A method according to claim 62 , wherein said step of forming conductive material within said via employs chemical-vapor-deposition.
 64. A method according to claim 62 , wherein said step of lining electrically couples a pit to conductive material in said via.
 65. A method according to claim 62 , wherein said step of forming conductive material in at least some of said pits comprises a step of depositing conductive material different from that within said via.
 66. A method according to claim 54 , further comprising a step of fixing a contact bump to an exposed surface of the conductive material in the via on a side of said substrate opposite said pocket.
 67. A method according to claim 66 , wherein said contact bump comprises a solder bump.
 68. A method according to claim 67 , wherein said contact bump comprises a tin/lead eutectic.
 69. An insert for interfacing an electronic device having a plurality of outwardly-projecting-contacts, said insert comprising: a substrate, walls of said substrate defining at least one pocket configured to receive an outwardly-projecting contact of the electronic device, other walls of said substrate defining a via through said substrate; conductive material disposed in said via; and second conductive material disposed in said at least one pocket, and over the conductive material in said via.
 70. An insert according to claim 69 , wherein said substrate comprises monocrystaline silicon.
 71. An insert according to claim 69 , wherein opposing walls that define said pocket are inclined with an angle of about 40-70 degrees relative a plane defined by a surface of said substrate.
 72. An insert according to claim 69 , wherein the walls defining said via adjoin a floor of said pocket.
 73. An insert according to claim 69 , further comprising dielectric between said conductive materials and said substrate.
 74. An insert according to claim 69 , further comprising an electrical-contact-bump disposed upon said substrate and over the region defined by where said via meets a surface of said substrate opposite said pocket.
 75. An insert according to claim 74 , wherein said electrical-contact-bump comprises solder.
 76. A BGA test socket for temporarily engaging a plurality of outwardly-projecting contacts of a BGA of a microelectronic device, said test socket comprising: a substrate, first walls of said substrate defining a pocket configured to seat an outwardly-projecting contact of the microelectronic device, and second walls of said substrate defining a passage through said substrate in communication with said pocket; first conductive material within at least a portion of said passage; and second conductive material conformably layered in at least a portion of said pocket and over said first conductive material.
 77. A BGA test socket according to claim 76 , wherein said substrate comprises silicon having a <100> lattice-plane of orientation at an outwardly facing surface thereof.
 78. A BGA test socket according to claim 76 , wherein sidewalls of said walls that define said pocket are sloped about 40-70 degrees relative a surface of said substrate.
 79. A BGA test socket according to claim 76 , wherein the walls defining said passage meet a wall of said walls defining said pocket.
 80. A BGA test socket according to claim 76 , further comprising a layer of insulating material between said first and said second conductive materials and said substrate.
 81. A BGA test socket according to claim 76 , wherein the walls of said passage meet a lower surface of said substrate to define an aperature and said BGA test socket further comprises a contact-bump fixed to said substrate over said aperature and electrically coupled to the first conductive material within said passage.
 82. A BGA test socket according to claim 81 , wherein said contact-bump comprises re-flowable conductive material.
 83. A BGA test socket according to claim 82 , wherin said contact-bump comprises a tin/lead alloy.
 84. A BGA test socket according to claim 82 , further comprising a support substate having a conductive contact pad, said substrate fixed to said support substrate with said contact-bump joined to said conductive contact pad.
 85. A BGA test socket according to claim 84 , wherein said substrate comprises mono-crystaline silicon and said support substrate comprises dielectric material.
 86. A method of forming a BGA socket for testing a microelectronic device comprisin a chip-scale-package having a plurality of outwardly-projecting-contacts, said method comprising steps of: providing a substrate; forming a pocket in said substrate configured to at least partially receive an outwardly-projecting-contact of said chip-scale-packaged microelectronic device; forming a via through said substrate; forming first electrically conductive material in said via; and depositing second electrically conductive material in at least a portion of said pocket, including a portion over the first electrically conductive material in said via.
 87. A method according to claim 86 , wherein said step of forming said pocket comprises forming sidewalls for said pocket that are sloped about 40-70° relative a surface of said substrate.
 88. A method according to claim 86 , wherein said substrate comprises monocrystaline silicon having a <100> lattice-plane of orientation at a surface thereof.
 89. A method according to claim 86 , further comprising a step of forming an insulating layer over said substrate including said pocket and said via.
 90. A method according to claim 89 , wherein said step of forming an insulating layer comprises a step of exposing said substrate to an oxidizing atmosphere.
 91. A method according to claim 86 , wherein said step of forming first conductive material in said via comprises a step of chemical-vapor-deposition.
 92. A method according to claim 86 , wherein said second electrically conductive material is different from said first electrically conductive material.
 93. A method according to claim 86 , further comprising a step of fixing said substrate to a support substrate with said pocket facing away from said support substrate.
 94. A method according to claim 86 , further comprising a step of forming a conductive-contact on a side of said substrate opposite said pocket, said conductive-contact coupled to a portion of said first electrically conductive material in said via.
 95. A method according to claim 94 , further comprising the steps of: providing a support substrate having a conductive-pad; and joining the conductive-contact of said substrate to the conductive-pad of said support substrate.
 96. A method according to claim 95 , wherein the conductive-contact of said substrate comprises a flowable metal alloy and the conductive-pad of said support substrate comprises conductive material wetable by said flowable metal alloy, and said step of fixing said substrate to the support substrate comprises the steps of: positioning the conductive-contact of said substrate in contact with the conductive-pad of said support substrate; heating and re-flowing the flowable metal alloy of the conductive-contact; and wetting the conductive-pad of said support substrate with the heated re-flow of said flowable metal alloy.
 97. A method according to claim 96 , wherein the first conductive material is selected to be wetable by reflow of the flowable metal alloy of said conductive-contact.
 98. A method according to claim 97 , wherein the second conductive material is different from said first electrically conductive material.
 99. A method according to claim 98 , wherein the second electrically conductive material is selected to resist bonding to the outwardly-projecting-contacts of a chip-scale-packaged microelectronic device.
 100. A method according to claim 98 , wherein the second electrically conductive material is selected to resist bonding to solder.
 101. A method according to claim 86 , wherein walls defining said via are formed substantially perpendicular to an upper surface of said substrate and sidewalls of said pocket are sloped with an angle between 40-70° relative to said upper surface.
 102. A method according to claim 101 , wherein the walls defining said via join a floor of said pocket.
 103. A method of testing a microelectronic device, said method comprising: providing a microelectronic device having a plurality of outwardly-projecting-contacts of a BGA; providing a test insert comprising a silicon substrate having walls that define a plurality of pockets configured to at least partially receive respective said plurality of outwardly-projecting-contacts, other walls of said silicon substrate defining a via extending through said silicon substrate, first conductive material in said via and at least a portion of at least one of said pockets, and a conductive-contact on a side of said silicon substrate opposite said pocket and electrically coupled to said pocket by way of said via; fixing said test insert to a support substrate with the conductive-contact of said test insert coupled to a conductive-pad of said support substrate; disposing said microelectronic device over said test insert with the plurality of pockets of said test insert removably coupled to respective ones of said plurality of outwardly-projecting-contacts of the microelectronic device; and propogating an electrical signal between said support substrate and said microelectronic device by way of said test insert.
 104. A method according to claim 103 , wherein the conductive-contact of said test insert comprises a flowable metal alloy and the conductive-pad of said support substrate comprises conductive material wetable by said flowable metal alloy, and said step of fixing said test insert to the support substrate comprises the steps of: positioning the conductive-contact of said test insert in contact with the conductive-pad of said support substrate, heating and re-flowing the flowable metal alloy of said conductive-contact, and wetting the conductive-pad of said support substrate with the re-flow of said flowable metal alloy.
 105. A method according to claim 104 , wherein the conductive-contact of said test insert comprises a solder bump.
 106. A method according to claim 103 , further comprising a step of forceably biasing said microelectronic device against said test insert to facilitate electrical coupling of the plurality of pockets of said test insert with respective ones of said plurality of outwardly-projecting-contacts of the microelectronic device. 